including:
* A BootRAM and bootloader
* Two independent bi-directional 2KB DataRAM buffers
* A High-Speed x16 Host Interface
* On-chip Error Correction

where Product failure could result in loss of life or personal or physical harm, or any military or defense application,.

5. Added CE don’t care state for Asynch Write, Load, Program, and Block Erase timing diagram 1. Corrected Errata 2. Added Copy-back Program Operation With Random Data Input 3. Pended Active Erase Current 4. Changed tBA from 11ns to 11.5ns Draft Date.

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